1. Field of the Invention
The present invention relates to a variable gain differential amplifier and a multiplication circuit.
2. Description of the Background Art
A variable gain differential amplifier (differential amplification circuit having a variable gain function) is employed in general. An integrated circuit employing Si (silicon) devices such as bipolar transistors and MOSFETs (metal oxide semiconductor field-effect transistors) mainly includes an amplifier having a Gilbert-cell structure or an OTA (operational transconductance amplifier) structure as the variable gain differential amplifier.
The amplifier having a Gilbert-cell structure has a wide variable gain range, but is inferior in power consumption and noise property. Therefore, a mobile communication device or the like generally employs an OTA structure having a variable resistance circuit formed by an FET switch and the like in a differential amplifier.
FIG. 20 is a circuit diagram of a conventional variable gain differential amplifier having an OTA structure.
The variable gain differential amplifier shown in FIG. 20 is formed by bipolar transistors (hereinafter simply referred to as transistors) 101 and 102, resistors 103, 104, 105 and 106 and an n-MOSFET (hereinafter simply referred to as an FET) 107. The FET 107 forms a variable resistance circuit 200.
The base of the transistor 101 is connected to an input terminal NI1 receiving an input signal RFin(+), and the base of the transistor 102 is connected to another input terminal NI2 receiving another input signal RFin(−). The input signals RFin(+) and RFin(−) are differential inputs. The collectors of the transistors 101 and 102 are connected to a power supply terminal NVC receiving a power supply voltage Vcc through the resistors 103 and 104 respectively. The emitters of the transistors 101 ad 102 are connected to ground terminals through the resistors 105 and 106 respectively. The collectors of the transistors 101 and 102 are connected to output terminals N01 and N02 respectively. Output signals RFout(+) and RFout(−) are derived from the output terminals N01 and N02 respectively. The output signals RFout(+) and RFout(−) are differential outputs.
The FET 107 is connected between nodes N1 and N2 connected to the emitters of the transistors 101 and 102 respectively. The gate of the FET 107 is connected to a control terminal NG receiving a control voltage AGC through a resistor 110.
In the variable gain differential amplifier shown in FIG. 20, the control voltage AGC is applied to the gate of the FET 107 for changing source-to-drain resistance of the FET 107, thereby performing gain control. When the FET 107 is brought into an ON-state, for example, the maximum gain and a low noise characteristic are attained. In this case, the variable gain differential amplifier is suitable for amplifying a small high-frequency signal. When the FET 107 is brought into an OFF-state, on the other hand, attenuation is maximized (minimum gain) to improve the distortion characteristic. In this case, the variable gain differential amplifier is resistant against cross modulation in a state having high electric field strength.
In the aforementioned variable gain differential amplifier, continuous gain control can be performed by varying the control voltage AGC supplied to the gate of the FET 107 forming the variable resistance circuit 200.
However, the variable resistance circuit 200 of the aforementioned variable gain differential amplifier has strong nonlinearity in a region of the control voltage AGC around a pinch-off voltage of the FET 107. Thus, the distortion characteristic is deteriorated in the vicinity of a specific control voltage level. When the FET 107 is supplied with the control voltage AGC at which waveform distortion is increased in continuous gain control, therefore, the distortion characteristic of the variable gain differential amplifier is deteriorated.
In the variable gain differential amplifier shown in FIG. 20, a high-frequency amplifier superior in dynamic range is implemented as the ratio of the impedance of the FET 107 in an OFF-state to the impedance in an ON-state is increased. It is ideal that the ON-state impedance (Zon) of the FET 107 reaches zero and the OFF-state impedance (Zoff) thereof is infinite.
However, the ideal state cannot be implemented due to finite ON-state resistance present in the ON-state of the FET 107 and finite OFF-state capacitance present in the OFF-state thereof.
FIG. 21(a) is a circuit diagram of the variable resistance circuit 200 of the variable gain differential amplifier shown in FIG. 20, FIG. 21(b) is an equivalent circuit diagram of the variable resistance circuit 200 with the FET 107 in an ON-state, and FIG. 21(c) is an equivalent circuit diagram of the variable resistance circuit 200 with the FET 107 in an OFF-state.
It is assumed that Ron represents the ON-state resistance of the FET 107 and Coff represents the OFF-state capacitance thereof.
The finite ON-state resistance Ron is present between the nodes N1 and N2 in the ON-state of the FET 107, while the finite OFF-state capacitance Coff is present between the nodes N1 and N2 in the OFF-state thereof. Thus, no ideal state can be implemented.
In general, the ON-state resistance Ron and the OFF-state capacitance Coff of the FET 107 are expressed as follows with the gate width Wg thereof:Ron=Ron(mm)/Wg(mm)  (1)Coff=Coff(mm)×Wg(mm)  (2)where Ron(mm) represents the ON-state resistance per 1 mm of the gate width Wg, and Coff(mm) represents the OFF-state capacitance per 1 mm of the gate width Wg. It is understood from the above equations (1) and (2) that the ON-state resistance Ron is reduced and the OFF-state capacitance Coff is increased when the gate width Wg is increased. It is also understood that the ON-state resistance Ron is increased and the OFF-state capacitance Coff is reduced when the gate width Wg is reduced.
If the gate width Wg of the FET 107 is increased to reduce the ON-state resistance Ron thereby improving a noise factor with respect to a small signal in the aforementioned conventional variable gain differential amplifier, the OFF-state capacitance Coff is increased in proportion to the gate width Wg to reduce the OFF-state impedance in a high-frequency domain when receiving a large signal. In other words, the distortion characteristic is deteriorated in this case. If distortion is preferentially reduced, the noise factor is disadvantageously deteriorated with respect to a small signal.